1. Field of the Invention
The present invention related to non-volatile programmable memory, and more particularly to non-volatile programmable memory having a buffering capability.
2. Description of Related Art
Byte programming for EEPROM (Electrically Erasable-Programmable Read-Only Memory) devices is longer than byte programming for EPROM (Erasable-Programmable Read-Only Memory) or Flash EPROM. In particular, byte programming requires about 5 ms for EEPROM as opposed to about 10 .mu.s for EPROM or Flash EPROM. The reason is that EEPROM devices typically use Fowler-Nordheim Tunneling mechanism to inject electrons or retrieve electrons to or from the floating gate, while EPROM or Flash EPROM devices typically use the CHE (channel hot electron) mechanism to inject electrons in the floating gate. The CHE mechanism is quite inefficient and typically requires anywhere from 100 .mu.A to 1 mA of programming current for each cell. This is why only one byte at a time is usually programmed in EPROM's or FLASH EPROM's devices. On the other hand, the FN (Fowler-Nordheim) tunneling mechanism barely consumes any current, being typically in the nanoamphere range. Because of this, many cells, illustratively a few thousand, can be programmed at the same time in parallel.
Because large number of cells can be programmed in parallel, page latches have been widely used in EEPROM devices to speed up their programming time. An early EEPROM device containing page latches is the type 28C64, which is a 64K EEPROM available from various manufacturers including Catalyst and Xicor. Each page latch is connected to a bitline; typically for a given EEPROM device, there are as many page latches as there are bitlines. For example, a 64K EEPROM (type 28C64) has 32 bytes of page latches, a 256K EEPROM (type 28C256) has 64 bytes of page latches, and a 1Mb EEPROM (type 28C010) has 128 bytes of page latches. A serial 8 Mbit Flash EEPROM type 26F080 available from Nexcom Technology, Inc. of Sunnyvale, Calif. has 536 bytes of page latches.
Page latches typically operate in the following way. The user provides to the memory the column address as well as the data byte followed by WE and CE to load the page latches. After all the page latches are loaded, the memory device goes into a self-timed programming cycle at the end of which the data in the page latches is transferred to the selected row decoded by the X-Address decoder. The device programming is sped up by a considerable factor. For example, if all 32 bytes are loaded in the page latches, the programming time per byte is cut from an average of 5 ms to 5 ms/32 or 156 .mu.s. For an 8 Mbit device having 2048 sectors of 536 bytes each, the average programming time is 5 ms/536 bytes or about 9 .mu.s.
A page latch has some features in common with an SRAM cell. For example, both page latches and SRAM cells typically includes two inverters connected back-to-back. However, page latches and SRAM cells have many differences as well. For example, SRAM cells are differential devices, while page latches are single ended. As a differential device, an SRAM cell is able to interact with high capacitance differential bit lines without affecting the value stored therein. However, as a single ended device, a page latch is not able to interact with a high capacitance line without potentially changing the value stored therein. While a page latch can be used as temporary storage before transferring data to a selected row of memory, a page latch is not usable as a data buffer.
One-transistor Flash EEPROM devices containing page latches have a further weakness, relative to regular EEPROM devices. Regular EEPROM devices, which contain two transistor memory cells, use a byte-select transistor for every byte, so that every byte is uniquely accessible. Eight page latches are associated with every byte, and an additional page latch is associated with the byte select. If only one byte needs to be modified, the modification can be easily achieved because only that byte will go through the Erase & Write cycle. However, Flash EEPROM devices using one-transistor memory cells have no byte-select transistors. If only one byte needs to be modified, the entire sector is erased (high threshold voltage V) and is subsequently entirely written. Typically, if a "Read-Modify-Write" operation is desired, the entire sector is read and stored in external RAM, the selected byte is modified, and the entire sector is loaded back into the page latches before the self timed Erase-Write Operation is initiated. Unfortunately, this process is time-consuming.
Memory devices containing page latches have a further weakness, which is problematical in some real time applications requiring continuous writes to memory. During programming of a sector in which data is transferred from the page latches to the selected sector, the page latches cannot be accessed until the sector programming is complete. Typically, a self-timed programming cycle takes about 5 ms. In a real time application generating sectors of data more frequently than once ever 5 ms, an external memory device must be used to temporarily store the stream of real time data until programming of the present sector is complete.